In FIG. 1, a prior art bit-select circuit comprises multiple address bytes organized into eight bits each. Semiconductor memory chips usually organize a memory array into rows and columns. Each row of memory array elements shares a connection commonly known as a wordline. Each column of memory array elements shares a connection commonly known as a bitline (B7, B6, . . . , B0). The specific intersection of a wordline and a bitline at a memory cell is used to provide a read and write capability for the cell. Typically, eight bitlines are organized as a byte, providing a conveniently sized grouping for handling data within the memory array.
Every bitline from the memory array is connected to peripheral logic outside the array by a passgate transistor. FIG. 1 includes eight pass-gate transistors (only three shown) contained within a bit-select multiplexer (“mux”). During a memory read operation, eight pass gates connecting eight bitlines of the same byte to the peripheral logic are enabled by a y-decoder output signal (e.g., decoder signal Y0 enables BYTE 0). When a subsequent eight bits of data are read, eight pass gates connecting eight bitlines of an adjacent byte are enabled by another y-decoder signal (i.e., decoder signal Y1 enables BYTE 1). The pass-gate transistors coupled to the decoder signals (Y0, Y1, Y127) are collectively known as the y-multiplexer or y-mux.
The bitline signals passed by the y-mux are connected in an organized fashion before being passed to a bit-select multiplexer. All B0 bits from bytes 0 . . . 127 are connected to a global bitline GBL0. Similarly, all B1 bits from bytes 0 . . . 127 are connected to a global bitline GBL1. Analogous connections are replicated with the remaining bitlines. The bit-select multiplexer selects one global bitline at a time during sensing, and couples the selected bitline to a sense amplifier SA.
However, the prior art bit-select multiplexer suffers from a deficiency as the memory size increases. Specifically, as the number of bytes in the memory page (also referred to as the memory page size) increases, the number of passgates connected to the global bitlines increases. This increases the electrical loading on the global bitlines, thus slowing down the sensing speed of the sense amplifier SA. Therefore, what is needed is a way to continually increase a number of bytes in a memory page while not increasing electrical loading on the bitlines, thereby maintaining the sensing speed of the sense amplifier.